For a liquid crystal display, organic EL display, or other flat panel display, plural scanning lines and plural signal lines are arranged crossing each other in a matrix configuration, and a pixel is arranged at each cross point of the matrix. By means of a scan driver LSI, the scanning lines are selected and driven in a line-sequential scheme. By means of a signal driver LSI, a display signal voltage (image information) is applied or written on each pixel on each selected scanning line so as to display an image.
FIGS. 5-7 illustrate an example of an organic EL display for a mobile phone (cell phone), etc. FIG. 5 is a front view of the display. FIG. 6 is a side view. FIG. 7 is a back view.
On said organic EL display 100, due to restriction of the assembly space, controller 106 for image display is arranged on printed board 104 on the back of display panel 102 by means of PCB (Print Circuit Board) assembly, and, at the same time, by means of TCP (Tape Carrier Package) assembly, scan driver LSI 108 and signal driver LSI 110 are arranged on films 112, 114, respectively, between printed board 104 and panel 102. For controller 106, one may also adopt FPC (Flexible Printed Circuit) assembly instead PCB assembly.
In consideration of the efficiency of laying wiring from scan driver LSI 108 and the restriction of the panel terminal pitch, the scan drive terminals ROWn connected to the scanning lines (not shown in the figure) on panel 102 can be divided into odd-numbered and even-numbered, and they are arranged on the left and right sides of panel 102, respectively. For example, the odd-numbered terminals ROW 2j-1 (j=1, 2, 3 . . . ) are on the left side of panel 102, while the even-numbered terminals ROW 2j are on the right side of panel 102. More specifically, if 176 scanning lines are provided, for example, on panel 102, as shown in FIGS. 5 and 7, along the left edge (or the right edge when viewed from the inner side) of panel 102, 88 odd-numbered scan drive terminals ROW1, ROW3, . . . ROW173, ROW175 are arranged as a longitudinal column, and, at the same time, along the right edge (or the left edge when viewed from the inner side) of panel 102, 88 even-numbered scan drive terminals ROW2, ROW4, . . . ROW174, ROW176 are arranged as a longitudinal column.
Also, signal drive terminals COL m connected to the signal lines (not shown in the figure) of panel 102 are arranged as a lateral row along the upper edge or the lower edge of panel 102. In this example, 432 signal drive terminals COL1, COL2, COL3, . . . COL431, COL432 are arranged corresponding to 432 signal lines.
As shown in FIG. 7, for scan driver LSI 108, too, TCP output terminals (leads) ROW1, ROW2, ROW3, . . . ROW174, ROW175, ROW176 are divided into odd-numbered output terminals (ROW1, ROW3, . . . ROW173, ROW175 and even-numbered output terminals (ROW2, ROW4, . . . ROW174, ROW176, and these two portions each are arranged as a column on the left and right sides, respectively. In this way, wiring to the odd-numbered scan drive terminals set along the left edge of the panel and wiring to the even-numbered scan drive terminals set along the right edge of the panel can be laid without crossing each other and at a high efficiency.
FIG. 8 is a diagram illustrating the configuration of terminals on the chip for scan driver LSI 108. As shown in the figure, said LSI 108 has a rod-shaped structure favorable to TCP. Along one edge extending in the longitudinal direction of the chip, the input terminals or pads (VSSOLED, VOLED, Vss, STV, . . . ) are arranged as a column. Along the opposite edge, output terminals or pads OUT1, OUT3, . . . OUT173, OUT175, OUT176, OUT174, . . . OUT4, OUT2 are arranged as a column.
As the principal input terminals or pads pertaining to this invention, VSSOLED and VOLED are terminals that take the driving L-level voltage (such as 0 V) and H-level voltage (such as 15 V) input to them from the power source circuit (not shown in the figure), respectively. VSS and VDD are terminals that have logic L-level voltage (such as 0 V) and H-level voltage (such as 3.3 V) input to them from the power source circuit, respectively. STV is a terminal that has the timing pulse indicating start of the frame or start pulse STV input to it from controller 106. L/R is a terminal that has control signal LR indicating the scanning order or scanning direction (forward/backward) of the scanning lines input to it from controller 106. CPV is a terminal that has clock CPV defining the line-sequential cycle for line-sequentially scanning the scanning lines input to it from controller 106.
The output terminal or pad group is divided into two types, that is, odd-numbered type OUT1, OUT3, . . . OUT173, OUT175 and even-numbered type OUT2, OUT4, . . . OUT174, OUT176, and they are [each] arranged as a column. The odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175 are arranged as a column in an order corresponding to said odd-numbered TCP output leads (ROW1, ROW3, . . . ROW173, ROW175. More specifically, the first output pad OUT1 is arranged at one end of the chip. Then, the third and later odd-numbered output pads OUT3, . . . OUT173, OUT175 are arranged in rising order with a prescribed spacing between them in the longitudinal direction (X-direction) of the chip. On the other hand, even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176 are arranged as a column in an order corresponding to said even-numbered TCP output leads (ROW2, ROW4, . . . ROW174, ROW176. More specifically, the second output pad OUT2 is arranged on the other end of the chip. Then, the fourth and later even-numbered output pads OUT4, . . . OUT174, OUT176 are arranged as a column in rising order with a prescribed spacing between them in the longitudinal direction (X-direction) of the chip.
FIG. 9 is a diagram illustrating the circuit constitution and layout of the main portion of scan driver LSI 108. FIG. 10 is a diagram illustrating in detail the circuit constitution and layout of FIG. 9.
As shown in FIG. 10, drive section 122 is arranged in the former section of output pad group 120, and selection section 124 is arranged in the former section of drive section 122. Drive section 122 has driver circuits DRi composed of decoders DECi and output buffers OUTBUFi corresponding to output pads OUTi (i=1, 2 , . . . 176, respectively. Selection section 124 has a shift register SR composed of flip-flops SREGi corresponding to various driver circuits DRi.
As far as the layout is concerned, odd-numbered output pad group OUT1, OUT3, . . . OUT173, OUT175 and even-numbered output pad group OUT2, OUT4, . . . OUT174, OUT176 are arranged at positions corresponding or opposite each other. In drive section 122, too, odd-numbered driver circuits DR1, DR3, . . . DR173, DR175 and even-numbered driver circuits DR2, DR4, . . . DR174, DR176 are arranged as two groups in the layout. By virtue of this layout of the odd-numbered and even-numbered types, the Nth output pad OUTi and the Nth driver circuit DRi are arranged in the same row in the Y-direction. Consequently, the output terminals of driver circuits DR1, DR3, . . . DR173, DR175, DR176, DR174, . . . DR4, DR2 are connected by wiring to output pads OUT1, OUT3, . . . OUT173, OUT175, OUT176, OUT174, . . . OUT4, OUT2 in parallel and free of crossing of wiring between each other.
On the other hand, flip-flops SREG1, SREG2, SREG3, . . . SREG174, SREG175, SREG176 of selection section 124 are not divided into odd-numbered and even-numbered types. Instead, from the first flip-flop SREG1 to the 176th flip-flop SREG176, they are arranged in increasing order as a column in the X-direction. Consequently, the output terminals of flip-flops SREG1, SREG2, SREG3, . . . SREG174, SREG175, SREG176 are connected by wiring to the input terminals of driver circuits DR1, DR2, DR3, . . . DR174, DR175, DR176 with wires crossing each other appropriately by means of a laminated wiring structure.
In this example, because the scanning lines are driven with respect to 3-value levels, that is, L-level, H-level, and HZ (high-impedance) level (high-resistance output H-level), three driving elements, such as driving transistors (not shown in the figure), are arranged in output buffer OUTBUFi of each driver circuit DRi. In order to turn on one of the three drive transistors in a selective way, three output terminals are arranged on decoder DECi, and three input terminals are arranged on output buffer OUTBUFi, respectively. Also, in order to get the timing needed for switching of said 3-value levels, not only the principal input terminal of decoder DECi is connected by wiring to the output terminal of the corresponding flip-flop SREGi, but the output terminals of adjacent flip-flops SREGi−1 and SREGi+1 are also connected by wiring to the input terminal for backward-direction selection of decoder DECi (LR=R) and the input terminal for forward-direction selection (LR=L).
Shift register SR of selection section 124 has a bidirectional data shift function. Start pulse STV indicating the start timing of the frame by controller 106 is selectively input corresponding to the scanning direction (forward/backward direction) to the data input terminals of flip-flops SREG1 and SREG176 at the two ends, respectively. The inverted output of adjacent flip-flop SREGi−1 or the inverted output of flip-flop SREGi+1 is selectively input to the data input terminal of each flip-flop SREGi except the two ends, depending on the scanning direction (forward/backward direction) through inverter INV. All of flip-flops SREG1, SREG2, SREG3, . . . SREG176 each have control signal LR indicating the scanning direction from controller 106 (forward/backward direction) input to the control terminal or the annexed controller, and, have the shift pulse or synchronization clock signal CPV having frequency of the line-sequential cycle input to the clock terminal.
FIG. 11 is a timing chart illustrating the waveforms or timing of the signals in the various parts in the circuit constitution shown in FIGS. 9 and 10. The examples shown in the figures are in the case in which the scanning direction is selected to forward-direction (LR=L).
At the start of each frame, H-level start pulse STV is input from controller 106 to first flip-flop SREG1 of selection section 124, at rise (CPV=1) of clock signal CPV, said start pulse STV is loaded or latched as shift data in flip-flop SREG1, and the output of flip-flop SREG1 is changed from H-level, which has been held up to this point, to L-level.
As the output of first flip-flop SREG1 is changed from H-level to L-level, corresponding to this change, the output of first driver circuit DR1 is also changed from inactive HZ-level, that is, the high-impedance H-level (15V), which has been held to this point, to active L-level (0 V). The drive voltage of said L-level selectively drives the first scanning line through output pad OUT1 and scan drive terminal ROW1. Here, the high-impedance H-level (15 V) means that a voltage of 15 V is output at a resistance as high as several MΩ. Also, H-level and L-level refer to outputs with a low resistance. On the other hand, the output of flip-flop SREG1 (L-level) is logically inverted by inverter INV, and it is then sent as the H-level shift data to the data input terminal of second flip-flop SREG2.
In the next clock cycle, when CPV rises (CPV=2), corresponding to this change, second flip-flop SREG2 latches the shift data from the preceding stage SREG1, and its output is changed from H-level, which has been held to this point, to L-level. For the flip-flops other than SREG2, L-level is latched at rise of CPV (CPV=2). Especially, the output of first flip-flop SREG1 returns from L-level, which has been held to this point, to H-level.
When the output of second flip-flop SREG2 is changed from H-level to L-level, corresponding to this change, the output of second driver circuit DR2 is also changed from inactive HZ-level, which has been kept to this point, to active L-level. The L-level drive voltage (0 V) selectively drives the second scanning line through output pad OUT2 and scan drive terminal ROW2. On the other hand, the output (L-level) of flip-flop SREG2 is logically inverted by inverter INV, and it is then sent as H-level shift data to the data input terminal of third flip-flop SREG3. Also, as a response to the change of the output of flip-flop SREG2 of the next stage from H-level to L-level, first driver circuit DR1 switches the drive voltage output to output pad OUT1 from the active L-level (0 V), which has been held until this point, to inactive H-level (15 V).
In the next clock cycle, as CPV rises (CPV=3), corresponding to this change, third flip-flop SREG3 latches the shift data from SREG2 of the preceding stage, and its output is changed from H-level, which has been held to this point, to L-level. For the flip-flops other than SREG3, L-level is latched at the rise of CPV (CPV=3). The output of second flip-flop SREG2 returns from L-level, which has been held until this point, to H-level.
When the output of third flip-flop SREG3 is changed from H-level to L-level, corresponding to this change, the output of third driver circuit DR2 is changed from inactive HZ level, which has been held until this point, to active L-level. The L-level drive voltage (0 V) selectively drives the third scanning line via output pad OUT3 and scan drive terminal ROW3. On the other hand, the output (L-level) of flip-flop SREG3 is logically inverted by inverter INV, and it is then sent as H-level shift data to the data input terminal of fourth flip-flop SREG4. Also, when the output of flip-flop SREG3 of the next stage is changed from H-level to L-level, second driver circuit DR2 has its output drive voltage return from active L-level to inactive H-level. Also, as a response to restoring the output of flip-flop SREG2 of the next stage from L-level to H-level, first driver circuit DR1 switches the output drive voltage from H-level to HZ-level.
In the later clock cycles, the same operation as described above is repeated for flip-flops SREG and driver circuits DR of the later stages. As a result, during one frame period, one by one, all of the scanning lines on panel 102 are sequentially driven selectively from the upper side or from the lower side in line-sequential cycles.
As already mentioned, between selection section 124 and drive section 122 in conventional scan driver LSI 108, the output terminals of flip-flops SREG1, SREG2, SREG3, . . . SREG174, SREG175, SREG176 extend in the X-direction and the Y-direction while their wiring lines cross one another in complicated ways, and they are connected by wiring to the input terminals of driver circuits DR1, DR2, DR3, . . . DR174, DR175, DR176. Consequently, size S of the wiring region in the Y-direction has to be rather large. Also, in order to control switching of the aforementioned 3-value output and scanning direction (forward/backward directions), three input terminals are arranged on each decoder DECi of each driver circuit DRi. In this case, the number of wires between selection section 124 and drive section 122 is tripled, and wiring region size S is doubled.
In this way, because the wiring region between selection section 124 and drive section 122 has a large size, the size of the chip in the Y-direction (chip width) becomes larger, and the chip area becomes larger. This is a problem.
In said conventional circuit constitution, it is believed that if decoders DEC1, DEC2, DEC3, . . . DEC174, DEC175, DEC176 of driver circuits DR1, DR2, DR3, . . . DR174, DR175, DR176 are arranged in the same order and in the same row with respect to flip-flops SREG1, SREG2, SREG3, . . . SREG174, SREG175, SREG176, one can change the shape and reduce the size S of the wiring region between them. However, even in this case, in order to compensate for the difference in the arrangement order between decoders DEC1, DEC2, DEC3, . . . DEC174, DEC175, DEC176 and output buffers OUTBUF1, OUTBUF3, . . . OUTBUF173, OUTBUF175, OUTBUF176, OUTBUF174, . . . OUTBUF4, OUTBUF2), plural wires have to be laid crossing each other in the X-direction and the Y-direction. As a result, in this case, it is necessary to set a large wiring region size in the Y-direction, and there is little change in the overall size of the chip.
Also, as shown in FIG. 12, the following layout has been proposed: Odd-numbered flip-flops SREG1, SREG3, . . . SREG173, SREG175 and even-numbered flip-flops SREG2, SREG4, . . . SREG174, SREG176 are arranged facing each other in the central portion; in an order corresponding to the order of odd-numbered flip-flops SREG1, SREG3, . . . SREG173, SREG175, odd-numbered decoders DEC1, DEC3, . . . DEC173, DEC175, odd-numbered output buffers OUTBUF1, OUTBUF3, . . . OUTBUF173, OUTBUF175, and odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175 are arranged on the right side, and, in an order corresponding to the order of even-numbered flip-flops SREG2, SREG4, . . . SREG174, SREG176, even-numbered decoders DEC2, DEC4, . . . DEC174, DEC176, even-numbered output buffers OUTBUF2, OUTBUF4, . . . OUTBUF174, OUTBUF176, and even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176 are arranged on the left side.
In the layout shown in FIG. 12, there is no need to have a large wiring region having plural wires crossing each other in a complicated way, and it is possible to halve the size in the X-direction. However, the size in the Y-direction is doubled. Also, in TCP, the size in the Y-direction (chip width) may be in the longitudinal direction of the tape, and the increase in the chip size in the longitudinal direction of the tape hampers winding-up of the tape reel (the chip is prone to breakage). Consequently, it is inappropriate for practical application.
The purpose of this invention is to solve the aforementioned problems of the prior art by providing an integrated circuit for scan driving that can significantly reduce the chip size.